`ifndef _ral_blk_REG_PRJ_sys_status_rtl_
`define _ral_blk_REG_PRJ_sys_status_rtl_

`include "vmm_ral_host_itf.sv"

`include "ral_reg_REG_PRJ_sys_status_base_status_rtl.sv"
`include "ral_reg_REG_PRJ_sys_status_blk_status_rtl.sv"


interface ral_blk_REG_PRJ_sys_status_itf();

logic [1:0] mode_in;
logic mode_rd;
logic [19:0] kernel_size_in;
logic kernel_size_rd;
logic [2:0] stride_in;
logic stride_rd;

logic [0:0] blk0_status_in;
logic blk0_status_rd;
logic [0:0] blk1_status_in;
logic blk1_status_rd;
logic [0:0] blk2_status_in;
logic blk2_status_rd;
logic [0:0] blk3_status_in;
logic blk3_status_rd;
logic [0:0] blk4_status_in;
logic blk4_status_rd;


modport regs(input mode_in,
             output mode_rd,
             input kernel_size_in,
             output kernel_size_rd,
             input stride_in,
             output stride_rd,
             input blk0_status_in,
             output blk0_status_rd,
             input blk1_status_in,
             output blk1_status_rd,
             input blk2_status_in,
             output blk2_status_rd,
             input blk3_status_in,
             output blk3_status_rd,
             input blk4_status_in,
             output blk4_status_rd);


modport usr(output mode_in,
            input mode_rd,
            output kernel_size_in,
            input kernel_size_rd,
            output stride_in,
            input stride_rd,
            output blk0_status_in,
            input blk0_status_rd,
            output blk1_status_in,
            input blk1_status_rd,
            output blk2_status_in,
            input blk2_status_rd,
            output blk3_status_in,
            input blk3_status_rd,
            output blk4_status_in,
            input blk4_status_rd);

endinterface



module ral_blk_REG_PRJ_sys_status_rtl(vmm_ral_host_itf.slave hst,
                                      ral_blk_REG_PRJ_sys_status_itf.regs usr);
reg hst_ack;
assign hst.ack = hst_ack;
reg [3:0] base_status_sel;
reg [3:0] blk_status_sel;

always @(*)
   begin
      base_status_sel = 'b0;
      blk_status_sel = 'b0;

      hst_ack = 0;

      if (hst.adr == 'h0) begin
         base_status_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'hc) begin
         blk_status_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
   end


wire [31:0] base_status_out;
ral_reg_REG_PRJ_sys_status_base_status_rtl base_status(hst.clk, hst.rstn,
                                                       hst.wdat[31:0], base_status_out, base_status_sel, hst.wen,
                                                       usr.mode_in,
                                                       usr.mode_rd,
                                                       usr.kernel_size_in,
                                                       usr.kernel_size_rd,
                                                       usr.stride_in,
                                                       usr.stride_rd);

wire [31:0] blk_status_out;
ral_reg_REG_PRJ_sys_status_blk_status_rtl blk_status(hst.clk, hst.rstn,
                                                     hst.wdat[31:0], blk_status_out, blk_status_sel, hst.wen,
                                                     usr.blk0_status_in,
                                                     usr.blk0_status_rd,
                                                     usr.blk1_status_in,
                                                     usr.blk1_status_rd,
                                                     usr.blk2_status_in,
                                                     usr.blk2_status_rd,
                                                     usr.blk3_status_in,
                                                     usr.blk3_status_rd,
                                                     usr.blk4_status_in,
                                                     usr.blk4_status_rd);


reg [31:0] _rdat;
always @(*)
   begin
      _rdat = 32'b0;
      unique casez ({|base_status_sel[3:0],
                    |blk_status_sel[3:0]})
         2'b1?: _rdat = base_status_out;
         2'b?1: _rdat = blk_status_out;
         default: _rdat = 32'b0;
      endcase
   end
assign hst.rdat[31:0] = _rdat;

endmodule
`endif
